Clock buffers — מק״טים

3.3-V LVPECL differential clock driver

1:9 differential LVPECL clock driver

1:9 differential LVPECL clock driver

200-MHz, 13-bit to 26-bit registered buffer with SSTL_2 inputs and outputs

500-MHz, 13-bit to 26-bit registered buffer with SSTL_2 inputs and outputs

500-MHz, 13-bit to 26-bit registered buffer with SSTL_2 inputs and outputs

25-bit configurable registered buffer with address-parity test

DB2000QL compliant 20-output clock buffer for PCIe® Gen 1 to Gen 7

Low jitter, 2-input selectable 1:16 universal-to-LVDS buffer

Low jitter, 2-input selectable 1:16 universal-to-LVDS buffer

Low jitter, 2-input selectable 1:8 universal-to-LVPECL buffer

Clock buffer with programmable divider, LVPECL I/O and LVCMOS output

Clock buffer with programmable divider, LVPECL I/O and LVCMOS output

1.8-V phase-lock loop clock driver with high output drive for DDR2 SDRAM applications

1.8-V phase-lock loop clock driver for DDR2 SDRAM applications

1.8-V/1.9-V phase-lock loop clock driver for DDR2 SDRAM applications

1.8-V/1.9-V phase-lock loop clock driver for DDR2 SDRAM applications

PLL clock driver for synch. DRAM & gen. purp. apps w/spread spectrum compatibility, power down mode

High performance 1:10 clock buffer for general purpose applications with support up to 85C

3.1-GHz differential clock buffer/level translator with 4 configurable outputs

Automotive, 1.5-V to 3.3-V, 1-to-4 high-performance LVCMOS fanout buffer & level translator

4-channel output LVCMOS 1.8-V buffer

Low additive jitter LVDS buffer

2-output LP-HCSL clock buffer for PCIe PCIe Gen 1 to Gen 7

4-output LP-HCSL clock buffer for PCIe PCIe Gen 1 to Gen 7

8-output LP-HCSL clock buffer for PCIe Gen 1 to Gen 7

8-output LP-HCSL clock buffer for PCIe Gen 1 to Gen 7

8-output LP-HCSL clock buffer for PCIe Gen 1 to Gen 7

DB2000QL-compliant 20-output clock buffer for PCIe Gen 1 to Gen 7

2-input 8-output LP-HCSL clock multiplexer for PCIe Gen 1 to Gen 7

2-channel output LVCMOS 1.8-V buffer for Automotive

500-MHz, 25-bit configurable registered buffer with SSTL_18 inputs and outputs

410-MHz, 25-bit configurable registered buffer with SSTL_18 inputs and outputs

28-bit to 56-bit registered buffer with address-parity test for heavily loaded DDR2 registered DIMMs

28-bit to 56-bit registered buffer with address-parity test

200-MHz, 13-bit to 26-bit registered buffer with SSTL_2 inputs and outputs

1-to-4 configurable low frequency clock buffer for 3D displays

3.3-V 6-bit inverter/clock driver

3.3-V 6-bit inverter/clock driver

5-V 6-bit inverter / clock driver

5-V 6-bit inverter / clock driver

5-V dual 1-to-4 clock driver

5-V dual 1-to-4 clock driver

5-V dual 1-to-4 clock driver

5-V dual 1-to-4 clock driver

1-line to 10-line clock driver with 3-state outputs